Tri-layered Heterostructure-On-Insulator System for FET at Nano Regime: Emerging Nanodevice Technology vol. I

The book discusses the development of new structure in Nanomaterial system with a 3-layered heterostructure technology system for implementation in MOS devices. A strained channel system technology is developed and initiated with layers such as strained-Si/strained-SiGe/strained-Si at the molecular level with detailed study and analysis of strain effect for the Type-II band-alignment mechanism being inserted in the thin channel layer of a FET. Thus establishing the development of the tri-layered heterostructure-on-insulator (HOI) system. On incorporating this HOI channel system in the regular MOSFET, devices performances were analysed based on electrical parameters, band strain effect, electric field, velocity overshoot, mobility and others. Extensive electron mobility relating to carrier enhancement is observed leading to superior drain current thus 93% performance enrichment achieved in comparison to the existing strained Si/SiGe MOSFETs of 50 nm gate length, for the 30 nm channel length HOI NanoFET.